Changes

- One In the previous tutorials, we said that our FPGA implementation of AES executes each round per of the algorithm in a single clock cycle. This probably means that there's one 128- Should be possible bit port used to apply glitches near store the internal state. On each clock edges- Causes cycle, this state is fed through a "fake" couple of different blocks (<code>SubBytes()</code>, <code>ShiftRows()</code>, <code>MixColumns()</code>, and <code>AddRoundKey()</code>), and the output is stored back into the state port.  Our goal in this tutorial is to cause the AES executionto fail by applying clock glitches. If we trigger a short clock glitch right next to a clock edge, overwriting we might be able to corrupt some of the bits of the state dataarray. If we can manage this, the output ciphertext will be totally different! Remember that one of the primary goals of cryptographic algorithms is diffusion: if we change a single bit of the input, the round function will cause that one bit to affect all 128 bits of the output.  In this tutorial, we'll say that a successful glitch is any glitch that causes the ciphertext to change. However, at the end of the tutorial, we'll look a bit deeper into the exact position and magnitude of these glitches to see exactly how our glitches are changing the output.